access after alias all assert architecture begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity signal shared subtype then to transport type unaffected units until use variable wait when while with note warning error failure ACCESS AFTER ALIAS ALL ASSERT ARCHITECTURE BEGIN BLOCK BODY BUFFER BUS CASE COMPONENT CONFIGURATION CONSTANT DISCONNECT DOWNTO ELSE ELSIF END ENTITY EXIT FILE FOR FUNCTION GENERATE GENERIC GROUP GUARDED IF IMPURE IN INERTIAL INOUT IS LABEL LIBRARY LINKAGE LITERAL LOOP MAP NEW NEXT NULL OF ON OPEN OTHERS OUT PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE RANGE RECORD REGISTER REJECT REPORT RETURN SELECT SEVERITY SIGNAL SHARED SUBTYPE THEN TO TRANSPORT TYPE UNAFFECTED UNITS UNTIL USE VARIABLE WAIT WHEN WHILE WITH NOTE WARNING ERROR FAILURE and or xor not AND OR XOR NOT bit bit_vector character boolean integer real time string severity_level positive natural signed unsigned line text std_logic std_logic_vector std_ulogic std_ulogic_vector qsim_state qsim_state_vector qsim_12state qsim_12state_vector qsim_strength mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector BIT BIT_VECTOR CHARACTER BOOLEAN INTEGER REAL TIME STRING SEVERITY_LEVEL POSITIVE NATURAL SIGNED UNSIGNED LINE TEXT STD_LOGIC STD_LOGIC_VECTOR STD_ULOGIC STD_ULOGIC_VECTOR QSIM_STATE QSIM_STATE_VECTOR QSIM_12STATE QSIM_12STATE_VECTOR QSIM_STRENGTH MUX_BIT MUX_VECTOR REG_BIT REG_VECTOR WOR_BIT WOR_VECTOR