summaryrefslogtreecommitdiff
path: root/qmake
Unidiff
Diffstat (limited to 'qmake') (more/less context) (show whitespace changes)
-rw-r--r--qmake/generators/unix/unixmake2.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/qmake/generators/unix/unixmake2.cpp b/qmake/generators/unix/unixmake2.cpp
index 1797b98..cbe2014 100644
--- a/qmake/generators/unix/unixmake2.cpp
+++ b/qmake/generators/unix/unixmake2.cpp
@@ -203,24 +203,25 @@ UnixMakefileGenerator::writeMakeParts(QTextStream &t)
203 t << endl; 203 t << endl;
204 } else { 204 } else {
205 moc_incremental = TRUE; 205 moc_incremental = TRUE;
206 t << endl; 206 t << endl;
207 t << "INCREMENTAL_OBJMOC = " << incrs_out.join(" \\\n\t\t") << endl; 207 t << "INCREMENTAL_OBJMOC = " << incrs_out.join(" \\\n\t\t") << endl;
208 } 208 }
209 } else { 209 } else {
210 t << "OBJMOC = " << objMoc << endl; 210 t << "OBJMOC = " << objMoc << endl;
211 } 211 }
212 if(do_incremental && !moc_incremental && !src_incremental) 212 if(do_incremental && !moc_incremental && !src_incremental)
213 do_incremental = FALSE; 213 do_incremental = FALSE;
214 t << "DIST = " << varList("DISTFILES") << endl; 214 t << "DIST = " << varList("DISTFILES") << endl;
215 t << "PRO = " << fileFixify(project->projectFile()) << endl;
215 t << "QMAKE_TARGET = " << var("QMAKE_ORIG_TARGET") << endl; 216 t << "QMAKE_TARGET = " << var("QMAKE_ORIG_TARGET") << endl;
216 t << "DESTDIR = " << var("DESTDIR") << endl; 217 t << "DESTDIR = " << var("DESTDIR") << endl;
217 t << "TARGET = " << var("TARGET") << endl; 218 t << "TARGET = " << var("TARGET") << endl;
218 if(project->isActiveConfig("plugin") ) { 219 if(project->isActiveConfig("plugin") ) {
219 t << "TARGETD = " << var("TARGET") << endl; 220 t << "TARGETD = " << var("TARGET") << endl;
220 } else if (!project->isActiveConfig("staticlib") && project->variables()["QMAKE_APP_FLAG"].isEmpty()) { 221 } else if (!project->isActiveConfig("staticlib") && project->variables()["QMAKE_APP_FLAG"].isEmpty()) {
221 t << "TARGETA= " << var("TARGETA") << endl; 222 t << "TARGETA= " << var("TARGETA") << endl;
222 if (os == "hpux") { 223 if (os == "hpux") {
223 t << "TARGETD= " << var("TARGET_x") << endl; 224 t << "TARGETD= " << var("TARGET_x") << endl;
224 t << "TARGET0= " << var("TARGET_") << endl; 225 t << "TARGET0= " << var("TARGET_") << endl;
225 } 226 }
226 else { 227 else {